Products
Hardware platforms and FPGA IP
JSE develops hardware platforms and reusable FPGA IP for SDR, RF, medical imaging, high-speed connectivity and low-latency data-acquisition systems.
General purpose products
VORTARIAN coherent multi-channel SDR transceiver
A scalable phase-coherent SDR platform for radar, phased-array, research and high-performance RF applications.
4 coherent RF receive channels
2 coherent RF transmit channels
16-bit ADCs at 500 MSPS
16-bit DACs at 1 GSPS
20 MHz to 1.4 GHz direct RF / IF sampling
Frequency coverage extendable up to 75 GHz with optional RF mezzanine front-ends
Dual 10GBASE-SR SFP+ interfaces
Efinix Titanium FPGA with Quad-Core RISC-V SoC
External 100 MHz reference clock
Technical specifications
| RF and data conversion | |
|---|---|
| Receive channels | 4 coherent RF channels, 50 Ω |
| Transmit channels | 2 coherent RF channels, 50 Ω |
| RF connectors | SMP standard; SMA available as an alternative option |
| ADC | 16-bit, 500 MSPS |
| DAC | 16-bit, 1 GSPS |
| Direct RF / IF sampling | 20 MHz to 1.4 GHz |
| Standard RX configuration | Optimized for 2nd-Nyquist-zone operation, 250 to 500 MHz; usable bandwidth is determined by the analog front-end filters. |
| Alternative RX bands | Customer-specific frequency ranges within the direct-sampling range available through LC filter adaptation. |
| ADC SFDR | >91.4 dBc at 404–406 MHz |
| RF front-end options | Application-specific RF mezzanine front-ends, extendable up to 75 GHz. |
| Processing and memory | |
| FPGA | Efinix Titanium Ti375 |
| Processor | Hardened Quad-Core 32-bit RISC-V |
| Memory | 2 × 8 Gb LPDDR4 |
| Clocking and synchronization | |
| External reference | 100 MHz external reference input |
| Internal reference | Ultra-low-phase-noise 100 MHz oscillator, ±25 ppm stability |
| Synchronization | Coherent multi-board synchronization capability |
| Connectivity and streaming | |
| Ethernet | 2 × 10GBASE-SR SFP+ |
| Data streaming | Continuous I/Q streaming after digital down-conversion |
| Software | GNU Radio compatible; MATLAB and Python integration supported |
| Power and mechanical | |
| Supply voltage | 10 to 14 V DC |
| Power consumption | 19 W typical; dependent on FPGA firmware configuration and workload |
| Board dimensions | 177 × 177 mm |
General purpose products
Two-channel RF signal generator
Direct-RF waveform generation with PCI Express connectivity for test, research and custom RF systems.
| RF signal generation | |
|---|---|
| DAC sampling rate | 12.5 GHz |
| RF output frequency range | 10 MHz to 5 GHz |
| Output architecture | Direct RF output without I/Q modulator impairments |
| Host interface | PCI Express Gen 2 |
| Fiber-optic interface | Optional PCIe over fiber optics |
| Waveform memory | Arbitrary I/Q waveform playback up to 100 Msamples |
Medical products
Multi-channel MRI scanner receiver
Direct-RF receiver platform with flexible channel count, high dynamic range, ultra-low-jitter clocking and customizable FPGA signal processing.
Flexible 8–48 channel architecture
Ultra-high SFDR >100 dB
Direct RF sampling
Fiber-optic PCI Express Gen 2 interface
Ultra-low-jitter clocking
Customizable FPGA signal processing
Low power consumption <20 W
Technical specifications
| RF and acquisition | |
|---|---|
| Number of channels | 8 to 48 receive channels |
| Sampling architecture | Direct RF sampling |
| SFDR | >100 dB |
| Clocking | Ultra-low-jitter clock architecture with external reference support |
| FPGA processing | |
| Signal processing | Customizable FPGA processing chain |
| System architecture | Multi-channel synchronous acquisition |
| Host connectivity | |
| Interface | Fiber-optic PCI Express Gen 2 |
| Software | Linux software interface |
| Mechanical and power | |
| Construction | Shielded receiver hardware |
| Power consumption | <20 W |
FPGA IP cores
Building blocks for high-speed FPGA systems
High-performance IP for data acquisition, communication, connectivity and low-latency FPGA processing.
JESD204B/C interface for ADC and DAC
• Lane speeds up to 15 Gbps
• 1 to 4 lane interface
• Support for high-speed ADC and DAC devices
• Deterministic latency and synchronization support
PCI Express interfaces with DMA support
• PCI Express Gen 2.x
• PCI Express Gen 3.0
• Bidirectional DMA between CPU memory and FPGA
• Up to x8 / x16 lanes
• PCIe over fiber-optics interface
• Built on more than 15 years of PCI Express FPGA development experience
FPGA modem and DSP IP cores
• Point-to-point radio modem building blocks
• Adaptive equalization
• FIR and IIR filtering
• Fractional interpolation and decimation
• Clock and sample-rate conversion
• Configurable DSP processing chains
• Adaptive timing recovery and carrier recovery loops
High-speed Ethernet and UDP IP cores
• 1 Gigabit and 10 Gigabit Ethernet interfaces
• Hardware UDP offload engines
• FPGA-based packet processing
• Sustained UDP streaming up to full 10 Gbps line rate
• Optimized for SDR, radio and high-speed data acquisition systems
• Built on nearly two decades of FPGA Ethernet and UDP streaming experience
Need a tailored hardware platform or FPGA IP core?
We can adapt interfaces, FPGA processing, synchronization and software around your system requirements.